1. Field of the Invention
Example embodiments of the present invention generally relate to a clock recovery circuit. In particular example embodiments of the present invention relate to a quarter-rate clock recovery circuit, and a method of recovering clock data using the same.
2. Description of the Related Art
In general, parallel circuits are more difficult to design than serial circuits. Therefore, in order to save costs in wiring and interconnection and/or to avoid noise, for example, a cross-talk noise associated with parallel circuits, a recent trend has been to transmit digital data between remote devices in a serial manner rather than in a parallel manner.
In a serial data transmission, data are serially transmitted through, for example, a single optical fiber, coaxial, or twisted-pair cable at a high speed. In a parallel data transmission, multiple lines are used to transmit several data streams simultaneously.
In order to reduce costs, a receiver may recover a clock from a bit stream of received high speed digital data using clock recovery circuit (CRC) instead of separately transmitting a clock synchronized with serial high speed digital data to a remote receiver. A conventional clock recovery circuit (CRC) may use a phase locked loop (PLL) or delay locked loop (DLL).
FIG. 1 is a block diagram illustrating a conventional clock recovery circuit using a phase locked loop (PLL).
A multiplexer 120 may receive a reference frequency clock 110 as an input. The reference frequency clock 110 may be generated by a crystal oscillator. The crystal oscillator may generate a relatively low frequency clock to provide to the multiplexer 120.
The reference frequency clock 110 may pass through a feedback loop to generate a high-frequency clock. The feedback loop may include a frequency phase detector 130, a loop filter 140, a voltage-controlled oscillator (VCO) 150, and/or a frequency divider 160.
When the oscillated high-frequency clock reaches a desired frequency, serial input data 100, and not the reference frequency clock 110, may be input to the phase locked loop (PLL) through the multiplexer 120.
A clock 180 synchronized to the serial input data 100 may be output from the VCO 150. The clock 180 may be applied to a flip-flop 170 with the serial input data 100, and a clock data 190 may be output from the flip flop 170.
In general, if a high-rate serial input data phase is input to a phase locked loop (PLL), and the high-rate serial input data has jitter, the PLL must be adapted to provide a clock synchronized to the high-rate serial input data in a short time.
Performance of the clock recovery circuit depends on the performance of the phase locked loop (PLL). However, it may be difficult to design a PLL capable of higher performance, because that may require a larger amount of power dissipation and/or a large chip area, which may increase noise.
A solution to the above problems may be phase interpolation.
Phase interpolation technology is a method of generating a clock having a phase between first and second phases of two input clocks. For example, a clock having a phase in a range from 0 degrees to 90 degrees may be generated based on a first clock having a phase of 0 degrees and a second clock having a phase of 90 degrees.
In particular, a half-rate clock recovery circuit that performs phase interpolation using four clocks is conventional.
The four clock recovery circuit may include a reference clock having a half frequency of input data and three clocks having a phase difference of 90 degrees, 180 degrees, and 270 degrees, respectively, with respect to the reference clock.
The half-rate clock recovery circuit may solve one or more difficulties in designing a circuit that operates at a higher speed by lowering its operating frequency.
There are at least two types of conventional half-rate clock recovery circuits, a first half-rate clock recovery circuit using at least two phase locked loops (PLLs) and a second half-rate clock recovery circuit using a single phase locked loop PLL, which generates four half-rate clocks I, Q, Ib, and Qb having 90 degree phase differences.
In order to broaden data bandwidth, the conventional half-rate clock recovery circuit may use a multi-channel configuration rather than a signal-channel configuration.
The half-rate clock recovery circuit of the multi-channel configuration may have transmitting/receiving channels in a parallel configuration, for example, parallel channels of 4, 8, 16, and so on.
The half-rate clock recovery circuit using at least two phase locked loops (PLLs) may require a larger amount of power dissipation and/or a larger chip area. In comparison, the half-rate clock recovery circuit using a single phase locked loop (PLL) generally may include a voltage-controlled oscillator (VCO) capable of generating a high frequency corresponding to an increased data transmission speed and an increased number of channels to generate four clocks having 90 degree phase differences with respect to each other to transmit the four clocks to each of the channels.
FIG. 2 is a block diagram illustrating a prior art or prior art publication date of Dec. 14, 1999 clock recovery circuit.
Serial input data 201 and a recovered clock 202 having a half rate to that of the serial input data 201 may be provided to a phase detector 210.
The phase detector 210 may compare a phase difference between two inputs 201 and 202, and output up/down signals 215 according to the comparison result.
The up/down signals 215 may be provided to a signal divider 220, and the signal divider 220 may output low-rate up/down signals 225, which can be available in a digital-to-analog converter (DAC) control logic 230.
The DAC control logic 230 may output digital control codes 235 based on the up/down signals 225 output from the signal divider 220, to perform a phase interpolation on the recovery clock 202.
The digital control codes 235 may be provided to a phase interpolation unit 250 via a plurality of digital-to-analog converters (DACs) 240.
The plurality of DACs 240 may include a non-linear DAC having a non-linear transfer characteristic to compensate for the non-linear characteristic of the digital control codes 235 when the digital control codes 235 output from the DAC control logic 230 are not linearly changed.
The phase interpolation unit 250 may perform a phase interpolation on four clocks 265 output from a clock generator 260 based on a weight control signal 245 output from the DAC 240, and may output the output clock 202 to track a phase of the serial input data 201.
The output clock 202 output from the phase interpolation unit 250 may be fed back to the phase detector 210. The half-rate clock recovery circuit may perform a phase interpolation on clocks having a half frequency of the serial input data 201.
For example, when a rate of the serial input data 201 is about 8.5 Gbps, the phase interpolation unit 250 performs a phase interpolation on first, second, third, and fourth clocks having a half frequency (4.25 GHz) of the serial input data 201. The second clock has a phase difference of 90 degrees with respect to a phase of the first clock, a third clock has a phase difference of 180 degrees with respect to a phase of the first clock, and a fourth clock has a phase difference of 270 degrees with respect to a phase of the first clock.
The phase detector 210 detects a phase difference between the 8.5 Gbps serial input data 201 and the first/second clocks, which are provided from the phase interpolation unit 250.
Alternatively, although not shown in FIG. 2, the phase detector 210 may multiplex the serial input data stream 201 into two data streams 270 having a half frequency of that of the serial input data stream 201 in order to recover data using the second clock having a phase difference of 90 degrees with respect to a phase of the first clock and a fourth clock having a phase difference of 270 degrees with respect to a phase of the first clock.
However, the conventional half-rate clock recovery circuit may have problems when the data-rate (or data transmission rate) increases.
There are at least two methods of generating four clocks having a half frequency (4.25 GHz) of that of the serial input data 201 and having phase differences of 90 degrees with each other to provide the four clocks to each of the channels as follows.
It is noted that a ring oscillator cannot be used to generate a frequency between 3 GHz through 4 GHz.
In a first method, when the data transmission rate is 8.5 GHz, a 8.5 GHz local voltage-controlled oscillator (VCO) may be implemented. The oscillated 8.5 GHz frequency may be divided by 2, and four clocks having a frequency of 4.25 GHz and having a phase difference of 90 degrees with each other may be generated using, for example, a flip-flop.
In the second method, when the data transmission rate is 8.5 GHz, four clocks having a frequency of 4.25 GHz and having a phase difference of 90 degrees with each other may be generated using, for example, a 4.25 GHz local voltage-controlled oscillator (VCO) and a poly-phase filter.
In both methods, four clocks having a phase difference of 90 degrees with each other are transmitted to each of the channels.
However, it may be difficult to implement a phase locked loop (PLL) that is operable at a relatively high frequency corresponding to the required data transmission speed and/or with the desired jitter characteristic.
Additionally, transferring the four clocks to each of the channels may cause a large power dissipation, mismatch between lines, and/or coupling effects, because power dissipation, mismatch between lines, and/or coupling effects may increase proportional to a frequency. Thus, transmission distance may be limited when clock buffer(s) are not used.
As the number of clock buffers increases, chip area and/or an amount of power dissipation increases, and thus a relatively larger package must be used. Also, the arrangement of a power voltage pad and a ground voltage pad may be considered in the floor plan of a chip.